The present invention relates to a method and a device for automatically performing a refresh operation in a semiconductor memory device, and in particular to a method and a device for automatically performing a refresh operation on a data of a memory cell in a semiconductor memory device such as a DRAM and a synchronous DRAM.
In order to stably maintain the data stored in the memory cell, the semiconductor memory device such as the DRAM and the SDRAM periodically or non-periodically carries out the refresh operation on the data according to a self refresh command or an auto refresh command.
FIG. 1 is a block diagram illustrating a structure of a conventional auto refresh circuit, and FIG. 2 is a timing diagram for explaining the generation of a buffer control signal according to a general clock enable signal.
A clock buffer 10 buffers an externally-inputted clock signal clk, and transmits it to an input buffer generator 14. A clock enable buffer 12 buffers an externally-inputted clock enable signal cke, and transmits it to the input buffer generator 14. When the semiconductor memory device reaches into a refresh mode, if the clock enable signal cke is at a high level, the auto refresh operation is performed. On the other hand, if the clock enable signal cke is at a low level, the self refresh operation is carried out.
The input buffer generator 14 receives signals from the buffers 10, 12, and outputs a control signal buffer_gen for enabling or disabling input buffers, such as a command buffer 16, an address buffer 24 and a data input buffer 26.
The command buffer 16 buffers the control signal buffer_gen from the input buffer generator 14 and externally-inputted signals, such as a TTL-level chip selection bar signal csb, a RAS bar signal rasb, a CAS bar signal casb and a write enable bar signal web, into a CMOS level in order to be internally used. A command decoder 18 decodes the signal from the command buffer 16. When the semiconductor memory device reaches into the auto refresh mode, the command decoder 18 transmits a signal aref having a predetermined level to a row active generator 20. Thereafter, a delay generator 22 receives a row active signal row_active from the row active generator 20, and transmits a signal rRAS_delay delayed as long as a RAS cycle time tRAS to the row active generator 20.
However, in general, the input buffers (command buffer 16, address buffer 24 and data input buffer 26) are turned on/off by the control signal buffer_gen generated in the input buffer generator 14 according to the state of the clock enable signal cke. Since the clock enable signal cke is at a high level in the auto refresh mode, the input buffers are normally operated.
When one input buffer is turned on, the current is a few tens .mu.A to a few hundreds .mu.A. One chip includes a few tens of input buffers. Accordingly, when the chip is in the refresh mode, the current flowing through the input buffer is a few mA to a few tens mA.
As a result, the input buffers receiving the external commands are unnecessarily operated in the auto refresh mode, which results in large power consumption.